| 摘要 |
A multiplier repeats an addition or subtraction between a first bit string representative of a product of multiplication and a second bit string representative of an addend or a subtrahend, wherein a saturation look-ahead circuit (20) checks predetermined high-order bits of the second bit string and bits at predetermined positions of a third bit string representative of the sum or the difference so as to predict saturated state in the accumulator (15), and a multiplexer (16) selects a fixed value when the saturation-Lockheed circuit predicts the saturated state, thereby accelerating the calculation. <IMAGE> |
