发明名称 INTERNAL CLOCK GENERATION CIRCUIT FOR SEMICONDUCTOR DEVICE
摘要 PURPOSE: An internal clock generator for a semiconductor device is provided to make a phase agreement rapidly within one period after receiving an external clock, and to generate an internal clock for maintaining a predetermined duty ratio of the external clock. CONSTITUTION: An internal clock generator includes a period determining part, an input buffer(100,500), a delay circuit(200,300,600), an output driving circuit and an output buffer(800). The period determining part receives a system clock before an external clock input, detects a delay time of the system clock, outputs a detection signal for determining a delay time of the external clock, and thus determining a delay time of the external clock. The input buffer buffers the external clock. The delay circuit has many delay circuits, and outputs many delay signals for delaying the external clock from the input buffer by a predetermined time, The output driving circuit receives the delay signals from the delay circuit, and outputs one delay signal among the delay signals according to the detection signal. The output buffer buffers the delay signal from the output driving circuit, and outputs the internal clock. Thereby, the internal clock generator for a semiconductor device makes a phase agreement within a rapid time of a minimum one period after receiving an external clock, and generates an internal clock for maintaining a predetermined duty ratio of the external clock.
申请公布号 KR20000065632(A) 申请公布日期 2000.11.15
申请号 KR19990012076 申请日期 1999.04.07
申请人 SAMSUNG ELECTRONICS CO, LTD. 发明人 KO, YUN HAK;KWON, O GYEONG
分类号 G11C7/00;(IPC1-7):G11C7/00 主分类号 G11C7/00
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