| 摘要 |
PURPOSE: A memory controller is provided to separate input data, delay separated data, and synchronize the delayed data group for processing normally the input data even though a data input speed is higher than a data process speed of a memory. CONSTITUTION: A memory controller comprises a clock generator(100), a data latching module(200), a data delay module(300), and a memory(400). The clock generator(100) separates a main clock signal supplied externally, supplies reference clocks at least more than one for the latching module(200) and the data delay module(300). The data latching module(200), including a plurality of latches(210,220,..), separates the data group signal according to the reference clock in response to a memory process speed, and transmits separated signals to the data delay module(300). The data delay module(300), including a plurality of data delayers(310,320,..), delays the separated data group signal for a set time according to the reference clock, synchronizes the delayed data signals and transmits the synchronized data signals to the memory(400).
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