| 摘要 |
PURPOSE: A data input buffer circuit is provided in which an inverter is configured of a transistor whose channel length is large when driven by a high external voltage for writing operation to compensate for data hold time and to reduce operation current. CONSTITUTION: A data input buffer circuit includes a NOR gate(NOR10) for NORing a data signal(DIN) received by a data input pad, a write enable signal(WE) and a chip selection signal(CS) to generate a control signal(WECS), a delay(100) whose delay rate is changed according to a high external power voltage(VCCH) or low external power voltage(VCCL) to delay the output of the NOR gate, an external power voltage detector(200) for detecting when an external power voltage(VCC) is high and low to generate a detection signal(PWDET) based on the detected result, and an inverter(INVB) for inverting the output of the external power voltage detector. |
