发明名称 |
Semiconductor device |
摘要 |
<p>A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part. <IMAGE></p> |
申请公布号 |
EP1052647(A2) |
申请公布日期 |
2000.11.15 |
申请号 |
EP20000109170 |
申请日期 |
2000.05.08 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
HONDA, YASUHIKO;KATO, HIDEO;SAITO, HIDETOSHI;KURIYAMA, MASAO;HARA, TOKUMASA;IKEDA, TAKAFUMI;HIRAMATSU, TATSUYA |
分类号 |
G11C16/00;G11C5/00;G11C8/12;G11C16/10;G11C16/26;(IPC1-7):G11C16/10 |
主分类号 |
G11C16/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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