发明名称 DYNAMIC CMOS CIRCUIT
摘要 PURPOSE: A dynamic CMOS circuit is provided to secure regardless of a delay time for deciding the period of an input signal, the pulse width of the input signal and the pulse width of an output signal in a semiconductor device for which the operation of high speed is demanded. CONSTITUTION: The circuit includes first and second connection points, a precharging circuit, a path forming circuit, a discharging circuit, an output terminal(T2) and a self-reset circuit(100). The first connection point has a reference voltage. The second connection point is precharged with a precharging state having a precharging voltage by accepting a plurality of charges and precharged with a discharging state having a discharging voltage by outputting the plurality of charges. The precharging circuit is connected to the second connection point and supplies the plurality of charges to the connection point. The path forming circuit is connected to the second connection point and supplies a conduction path for the plurality of charges outputted from the connection point. The discharging circuit is connected between the path forming circuit and the reference connection point, accepts a logic signal and discharges the plurality of charges outputted from a precharge connection point through the conduction path of the path forming circuit according to the logic signal. The output terminal is connected to the second connection point through the first inverter. The self-reset circuit has a delay circuit(160) for deciding duration of the discharging state, discharges the output terminal through the second connection point and the inverter during the duration decided by the delay circuit when the logic signal is activated and then precharges the output terminal through the second connection point and the first inverter. The self-reset circuit makes so that the precharging operation for maintaining an operation standby state of the path forming circuit and corresponding to the latter is performed regardless of the delay time of the delay circuit before the logic signal is reactivated.
申请公布号 KR100272672(B1) 申请公布日期 2000.11.15
申请号 KR19970081005 申请日期 1997.12.31
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 CHUNG, MIN-CHOUL;JUNG, CHUL-MIN
分类号 G11C11/40;H03K19/017;H03K19/096;(IPC1-7):G11C11/40 主分类号 G11C11/40
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