| 摘要 |
An EDA tool is provided with a placement and routing (P&R) module that optimizes placement and routing of an IC design in an interconnect delay driven manner. The P&R module systematically determines if it can improve (i.e. reduce) interconnect delay of the current critical interconnect routing path by determining if it can improve the interconnect delays of its constituting segments, each interconnecting two pins through a component. For each segment, the P&R module determines if the interconnect delay can be achieved by using different interconnect routing path interconnecting the two pins through the component replaced at a different location, and alternatively, through a logically equivalent component disposed at a different location. |
