| 摘要 |
An electronic circuit simulator technique dramatically reduces barriers to simulation of complex analog circuits. The invention reduces simulation preparation time by permitting as killed user to formulate a simulation strategy that can combine a modeling strategy, a deck extraction strategy, and a comprehensive suite of pre-engineered simulation tests that fully characterize a system under test. This pre-engineered simulation strategy can be applied to a new system very quickly in an automated fashion by a circuit designer having much less simulation experience than that of the skilled user who formulated the simulation strategy. The invention reduces the CPU time required for each test by allowing a skilled user to encode a device modeling strategy and a deck extraction strategy that effectively minimize the CPU time required to achieve a given simulation objective. For a given simulation objective, as killed user chooses for each element implemented in a simulation a device model of minimum complexity that achieves a desired level of simulation accuracy and extracts a portion of the complete production schematic that achieves the desired level of simulation accuracy. The invention reduces dramatically the effort required of a user to compose a required number of inputs to run a specified number of simulation tests and reduces dramatically the amount of CPU time required to run them. |
