| 摘要 |
PROBLEM TO BE SOLVED: To reduce a phase error in a delayed lock loop by coupling at least one of plural delay line outputs of buffer circuits with a reference clocking signal so that the error is averaged at least over two of phases established by plural buffer circuit outputs. SOLUTION: The reference clocking signal supplied to a delay line 47a and a phase detection/control device 48 via connection 24 is delayed so as to constitute quadrature phase outputs and the quadrature phase outputs X[0], X[1], X[2], X[3] are supplied on each of connection 53a, 53b, 53c, 53d by delay lines 47a, 47b, 47c and 47d. The outputs of each delay line indicate boundaries between two continuous phases here. The error is averaged over plural phases so that all of the errors to be generated in the reference clocking signal are not concentrated on one phase and the error generated in the output X[3] due to either of the error of the reference clocking signal or the quadrature phase output is averaged at least over two phases. |
