| 摘要 |
A fractional-N frequency synthesiser having an increased range of fractional control values outside the usual range {0,1}. The synthesiser is based on a PLL having a frequency divider controlled by an improved modulator system. Noise and fractional spurs in the output of the PLL are reduced. The modulator includes a multi-level quantiser with additional logic operations in output and feedback stages. A cascade of modulators may be used. A dither signal may be added as required within one or more of the modulators. |
