发明名称 |
DRAM cell arrangement and method for its production |
摘要 |
A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.
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申请公布号 |
US6147376(A) |
申请公布日期 |
2000.11.14 |
申请号 |
US19990228611 |
申请日期 |
1999.01.12 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
HOFMAN, FRANZ;RISCH, LOTHAR;ROESNER, WOLFGANG;KRAUTSCHNEIDER, WOLFGANG |
分类号 |
H01L21/8242;H01L27/108;(IPC1-7):H01L27/108 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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