发明名称 Add compare select circuit and method implementing a viterbi algorithm
摘要 A detector system employing a Viterbi algorithm includes an apparatus and method which constructs a double-state trellis structure for determining a most likely received symbol sequence with respect to an observed sequence of channel output samples. In the double state trellis, pairs of states are identified having equivalent branch metric values which also have a same decision during a path select, thus allowing these pairs of states to share a compare operation of a previous state metric. Consequently, to calculate an updated or current state metric value, an add, compare and select (ACS) circuit may compare only the previous state metric values to determine a minimum value for a transition between two states while combining each previous state metric value with its corresponding branch metric to provide an updated or current state metric value.
申请公布号 US6148431(A) 申请公布日期 2000.11.14
申请号 US19980049158 申请日期 1998.03.26
申请人 LUCENT TECHNOLOGIES INC. 发明人 LEE, INKYU;SONNTAG, JEFFREY LEE
分类号 G06F11/10;H03M13/23;H03M13/41;(IPC1-7):H03M13/03 主分类号 G06F11/10
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