发明名称 |
Hierarchical bus simple COMA architecture for shared memory multiprocessors having a bus directly interconnecting caches between nodes |
摘要 |
A method of maintaining cache coherency in a shared memory multiprocessor system having a plurality of nodes, where each node itself is a shared memory multiprocessor. With this invention, an additional shared owner state is maintained so that if a cache at the highest level of cache memory in the system issues a read or write request to a cache line that misses the highest cache level of the system, then the owner of the cache line places the cache line on the bus interconnecting the highest level of cache memories.
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申请公布号 |
US6148375(A) |
申请公布日期 |
2000.11.14 |
申请号 |
US19980023754 |
申请日期 |
1998.02.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BAYLOR, SANDRA JOHNSON;HSU, YARSUN |
分类号 |
G06F12/08;G06F15/16;G06F15/177;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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