发明名称 CONTROL PULSE GENERATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To simplify a decode circuit and to make timing management of a control pulse easier by generating a count up signal where an input signal and a phase are synchronized, decoding the signal and generating a control pulse necessary to signal processing. SOLUTION: A control pulse (f) which is synchronized with a phase of an input signal (a) is prepared by a decode circuit 5 by using a count up signal (e) from a counter circuit 4 and inputted to a signal processing circuit 1 together with the input signal (a). In a signal processing circuit 11, this input signal (a) is applied by the signal processing and an output signal (b) is outputted after a delay A is elapsed. The control pulse (f) is added to the delay A and outputted as a control pulse (g). Since the phases of the output signal (b) and the control pulse (g) are the same, it is possible to input them to a next step signal processing circuit 22. When a change occurs to processing contents of the signal processing circuit 11, the delay time A to be added to the control pulse (f) is changed accordingly.
申请公布号 JP2000316103(A) 申请公布日期 2000.11.14
申请号 JP19990125796 申请日期 1999.05.06
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KAWABATA MINORU;TAKAGI MASAMITSU
分类号 H04N5/06;(IPC1-7):H04N5/06 主分类号 H04N5/06
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