Method of forming a DRAM device utilizing a sacrificial doped oxide layer

摘要

A DRAM cell includes a transfer FET on a substrate and includes a charge storage capacitor formed using a process that avoids high temperature processing steps and which emphasizes low cost processes. The transfer FET is covered with a conformal sacrificial layer of doped oxide, preferably phosphorus silicate glass. A contact opening is formed through the layer of doped oxide to expose one of the source/drain regions of the FET and a doped polysilicon layer is deposited over the layer of doped oxide and in contact with the source/drain region. The layer of conductor is patterned to define the lateral extent of at least a portion of the lower electrode and then the doped oxide layer is removed from between the gate electrode and the polysilicon layer in a wet etching process. Particularly when this wet etching process removes the preferred phosphorus silicate glass sacrificial layer, this process can be accomplished at high speed and with minimal process complexity. Further processing provides a capacitor dielectric on upper and lower surfaces of the layer of conductor and provides an upper capacitor electrode.