发明名称 METHOD FOR FORMATION OF VIA HOLE AND MANUFACTURE OF MULTILAYERED WIRING BOARD
摘要 <p>PROBLEM TO BE SOLVED: To provide a method by which via holes having desired shapes can be formed in a reduced number of steps by preventing the occurrence of air traps or the disconnection of a conductor wiring section in a conductor wiring forming process, etc. SOLUTION: First, an insulating section 3 composed of a negative resist is exposed by using a photomask 5 for carrying a light shielding film 4 which intercepts exposure light beams L, and a transmittance adjusting film 11 which is arranged outside of the film 4 and changes the transmittance of the light beams L. Then a via hole 8, which becomes wider in width as going toward its opening, is formed by developing the exposed insulating section 3 with a developing solution 7.</p>
申请公布号 JP2000315868(A) 申请公布日期 2000.11.14
申请号 JP19990123156 申请日期 1999.04.28
申请人 NEC IBARAKI LTD 发明人 KASUYA KAZUHIRO
分类号 H05K3/00;G03F1/00;G03F1/68;G03F7/20;H01L21/027;H05K3/46;(IPC1-7):H05K3/46;G03F1/08 主分类号 H05K3/00
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