MEMORY CONTROL USING MEMORY STATE INFORMATION TO SHORTEN ACCESS LATENCY TIME

摘要

PROBLEM TO BE SOLVED: To provide memory control and access traffic control for shortening memory access latency time. SOLUTION: A memory controller circuit 18a connected to a memory 24 consisting of plural lines includes a circuit 28 for receiving a signal expressing a memory access request. The 1st signal received by the receiving circuit 28 includes the 1st address and the 2nd signal received by the circuit 28 after the reception of the 1st signal includes the 2nd address of the memory. The circuit 18a includes also a determination circuit 30 (RAn, AC#Bn#ROW, C#B#Rn) for determining whether the 2nd address is related with the 1st address or not and a circuit 30 for issuing a control signal to the memory 24. Each memory access is generated by the control signal in response to each request. The control signal issuing circuit 30 issues the control signal to the memory 24 so that the same line out of plural lines is actively stored between the 1st and 2nd accesses in response to the determination circuit 30.