| 摘要 |
PROBLEM TO BE SOLVED: To provide a data rate conversion circuit capable of converting a data rate without being influenced by the timing of input and output clock signals and without generating an error in output data. SOLUTION: A counter 10 counts up input clock signals CKA and outputs an input count value CNA. A write control signal WEN or the like is generated in accordance with the input count value CNA and input data SID is written in a RAM 1. When prescribed write data WDT are written in the RAM 1, a ready signal RDY having pulse width of two cycles or more of an output clock signal CKB is outputted from a read starting part 50. When the ready signal RDY is provided, a read control part 60 generates a start signal TRG at the rise of the 2nd clock of the output clock signal CKB to start up a counter 70. Consequently data in the RAM 1 are read out at prescribed timing and outputted as output data SOD synchronously with the output clock signal CKB. |
