发明名称 FORMATION OF LAYOUT OF PATTERN FOR LSI, FORMATION OF PATTERN FOR LSI AND FORMATION OF MASK DATA FOR LSI
摘要 <p>PROBLEM TO BE SOLVED: To make it possible to surely execute the proximity effect correction capable of forming a circuit pattern to enable operation while subjecting an LSI(large-scale integrated circuit) to desired fining. SOLUTION: This method for formation of a layout consists in first setting a design rule, basic process conditions, etc., (SB1). Next circuit patterns are formed in accordance with the set design rule (SB2) and thereafter, whether the formed circuit patterns satisfy the design rule or not is certified (SB3). OPC (proximity effect correction) pattern forming specifications are then set (SB5) and the OPC patterns are formed from the respective circuit patterns in accordance with the OPC pattern forming specifications (SB6). Whether the formed OPC patterns satisfy an OPC pattern arrangement rule or not is certified (SB7). Whether an OPC effect may be obtained or not is certified (SB10). If the OPC pattern arrangement making it infeasible to obtain the OPC effect is decided to exist (SB11), the design rule is so corrected as not to generate the OPC pattern arrangement making it infeasible to obtain the OPC effect (SB12).</p>
申请公布号 JP2000314954(A) 申请公布日期 2000.11.14
申请号 JP20000048766 申请日期 2000.02.25
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MITSUSAKA AKIO;ODANAKA SHINJI
分类号 H01L21/027;G03F1/36;G03F1/68;G03F1/70;G06F17/50;(IPC1-7):G03F1/08 主分类号 H01L21/027
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