| 摘要 |
When a program of a DSP 104 and address initial values "AH0" and "AL0" are stored to a ROM 101 and control to transfer the program to a command RAM 108 of the DSP 104 in a state that the stored address initial values are set at the top are executed by a CPU 102 comprising a control signal generating section 103, a ternary counter 105, which repeats a number count operation corresponding to a data length (for example, 3 bytes) of the command RAM 108, performs a count in accordance with a clock signal generated from a control signal generating section 103, while an address counter 106 loads the address initial values of the ROM 101, and then increments the address value for each count-up of the ternary counter 105 and outputs the resultant to the command RAM 108. <IMAGE> |
