INTEGRATED CIRCUIT, METHOD OF MANUFACTURE THEREOF, AND METHOD OF PRODUCING MASK PATTERN

摘要

Large capacitance for voltage stabilization is provided without increases in areas and interconnections. Large capacitors (C) for source voltage stabilization are formed at points where the lines at a first potential (Vss) on a fifth wiring layer (M5) intersect with the lines at a second potential (Vdd) on a fourth wiring layer (M4) and at points where the lines at the second potential (Vdd) on the fifth wiring layer (M5) intersect with the lines at the first potential (Vss) on the fourth wiring layer (M4). The capacitor (C) is distributed substantially uniformly in the inner region (1a) of a semiconductor substrate (1) (chip).