TRENCH CAPACITOR DRAM CELL WITH VERTICAL TRANSISTOR

摘要

A DRAM cell is disposed in an electrically isolated region of a semiconductor body. The cell includes a storage node (30) disposed in a trench. The node is disposed entirely within the isolated region of the semiconductor body. The cell includes a transistor (T) disposed in the isolated region. The transistor has a pair of gates (61, 62). A word line (WL) is provided for addressing the cell. The word line has a pair of contact regions (24, 25) to the transistor gates. The word line contact region is disposed entirely within the isolated region of the semiconductor body. The transistor has an active area. The active area has source (S), drain (D), and channel (C) regions. The active area is disposed entirely within the isolated region of the semiconductor body. A bit line is provided for the cell. The bit line is in electrical contact with the source of the transistor at a bit line contact region (20), disposed entirely within the isolated region of the cell. With such an arrangement a DRAM cell is provided having a relatively small amount of surface area of the semiconductor body.