| 摘要 |
<p>A clock signal generator (128) for generating N sub-sampling clock signals from a master clock signal, and an analog sampling circuit (140) and analog-to-digital convener (100) incorporating same. Each of the sub-sampling dock signals generated by the clock signal generator has fast and precisely-timed edges. The clock signal generator comprises a clock window signal generating circuit (149) and N gate circuits (e.g., 151), where N is an integer greater than unity. The clock window signal generating circuit is connected to receive the master dock signal and derives N dock window signals having imprecisely-timed edges from the master clock signal. Each of the N gate circuits generates one of the sub-sampling clock signals with logic states defined by one of the clock window signals and with edge timings defined by the master clock signal independently of the imprecisely-timed edges of the clock window signal, and includes a first input (e.g., 159), a second input (e.g., 167) and an output (169). The first input is connected to receive the clock window signal, the second input is connected to receive the master clock signal, and the output provides the sub-sampling clock signal. <IMAGE></p> |
