发明名称 |
An instruction supply mechanism |
摘要 |
An instruction prefetch buffer is described which has a powersave mechanism. A set of output devices of an instruction supply mechanism each have a stop switch which either pass on a changed bit sequence or the previously supplied bit sequence. If the previously supplied bit sequence is supplied, no power is utilised in that machine cycle. <IMAGE>
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申请公布号 |
EP1050801(A1) |
申请公布日期 |
2000.11.08 |
申请号 |
EP19990410051 |
申请日期 |
1999.05.03 |
申请人 |
STMICROELECTRONICS S.A. |
发明人 |
WOJCIESZAK, LAURENT;COFLER, ANDREW |
分类号 |
G06F9/30;G06F9/318;G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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