CMOS semiconductor integrated circuit

摘要

In order to reduce power consumption, a power supply for a digital circuit portion is shut off, so that the output voltage of the power supply becomes the zero level. A CMOS (complementary metal oxide semiconductor) inverter (10) has a P-channel FET (field effect transistor)(11) with a gate electrode formed of P-type polysilicon. A source electrode of the P-channel FET (11) is connected to the power supply and a back gate electrode of the P-channel FET (11) is in direct connection with the aforesaid source electrode. The P-channel FET (11) is placed in a state of not functioning as a transistor when the power supply is shut off in a low power consumption mode. However, in order to prevent the P-channel FET (11) from undergoing characteristic degradation in that mode, there is the provision of a pull-down switch (24) capable of fixing, in the mode, the voltage of the gate electrode of the P-channel FET (11) at the zero level.