发明名称 Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation
摘要 A method for forming a dual inlaid contact structure (damascene) begins by etching dual inlaid contact structures (32, 34, and 36). Masking layers (28) are (228) and the deposition of low-K dielectric material 26 is used to selectively form low-K regions (30) only in critical areas where low-K dielectric material is absolutely needed. Other portions of the wafer remain covered with conventional oxide (24) so that adverse impacts of low-K dielectric material is minimized. Conductive material (38, 40, and 42) is then formed to complete dual inlaid contact structures whereby low-K dielectric plugs (30) reduce cross talk and capacitance within the final structure.
申请公布号 US6143646(A) 申请公布日期 2000.11.07
申请号 US19970868332 申请日期 1997.06.03
申请人 MOTOROLA INC. 发明人 WETZEL, JEFFREY THOMAS
分类号 H01L21/3105;H01L21/316;H01L21/768;(IPC1-7):H01L21/476 主分类号 H01L21/3105
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