Circuit and method for a multiplexed redundancy scheme in a memory device

摘要

A semiconductor memory device including a memory-cell array divided into a plurality of memory sub-arrays that are arranged into rows and columns of memory cells. Each of the sub-arrays have a limited number of redundant rows and columns to repair defective memory cells. The redundant memory of at least two memory sub-arrays are coupled to an I/O line through a respective isolation circuit. A control circuit coupled to the isolation circuits selectively couples the redundant memory of the sub-arrays to the I/O line. Coupling the redundant memory of multiple sub-arrays facilitates using the redundant memory of one sub-array to repair the defective memory cells in other sub-arrays also coupled to the I/O line, when the redundant memory primarily associated with the other sub-arrays have been depleted.