发明名称 Semiconductor memory device
摘要 As the pre-charge potential for write global data buses (12, 13), a potential lower than the power supply voltage (Vii) for peripheral circuit by the threshold voltage (Vth) of a transistor is used. This suppresses disturbance in the potential of a pair of bit lines (18, 19) due to pre-charge operation. It suffices if the write global data buses are pre-charged to the potential lower than the power supply voltage (Vii) for peripheral circuit by the threshold voltage (Vth). This can reduce current consumption accordingly. By generating the pre-charge potential without using the power supply voltage (Viic) for core, adverse effects on sense operation can be avoided.
申请公布号 US6144602(A) 申请公布日期 2000.11.07
申请号 US20000493624 申请日期 2000.01.28
申请人 FUJITSU LIMITED 发明人 UZAWA, YUICHI
分类号 G11C11/409;G11C7/10;G11C7/12;G11C11/4094;G11C11/4096;(IPC1-7):G11C7/00 主分类号 G11C11/409
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