发明名称 TEST CIRCUIT AND TEST METHOD FOR SEMICONDUCTOR DEVICES
摘要 PROBLEM TO BE SOLVED: To provide a test circuit and test method for semiconductor devices capable of function tests and d-c tests and enable an LSI tester with a few of pins to test. SOLUTION: A test circuit for multi-pin type LSIs designed for boundary scan tests comprises a control circuit 5, input buffer d-c test circuits 1p-1r, output buffer d-c test circuits 2p-2r and a d-c test judging circuit 6 whereby d-c tests can be made at input buffers 11p-11r and output buffers 12p-12r, without directly connecting external input/output terminals 5A3, 5B3 to tester pins 71l-71m.
申请公布号 JP2000310668(A) 申请公布日期 2000.11.07
申请号 JP19990119039 申请日期 1999.04.27
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 HATAKEYAMA SHIGERU
分类号 H01L21/822;G01R31/28;G01R35/00;H01L21/66;H01L27/04;(IPC1-7):G01R31/28 主分类号 H01L21/822
代理机构 代理人
主权项
地址