| 摘要 |
A nonvolatile memory of a hierarchical bit line structure having hierarchical bit lines constituted by a plurality of sub-bit lines. Each sub-bit line is connected to an appropriate main bit line through a first and a second selection MISFET, the first selection MISFET having a thin gate insulating film and used for read operations only, the second MISFET having a thick gate insulating film and used at least for write operations. In a write operation, the first selection MISFET has its drain or its gate supplied with a predetermined bias voltage so that the gate insulating film of the transistor will not be subject to a voltage defeating the dielectric strength of the film.
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