| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide an image processor capable of displaying an SIF image signal to be magnified/reduced without degrading image quality and unnecessitating an image memory large in scale thereby making the processor small in circuit scale and low in cost. SOLUTION: An SIF decoder demodulates an SIF image of the MPEG-1 system to obtain a 3OP image. A horizontal vertical magnification reduction circuit 6 applies two-dimensional processing to the 3OP image to magnify or reduce the image in horizontal and vertical directions. A 3OP-6OI conversion circuit 7 receives an output signal from the horizontal vertical magnification/ reduction circuit 6, converts the signal into a 6OI image and outputs the image. Furthermore, a decoder 2 is provided with at least one of an MP ML decoder 4 demodulating an MP ML image of the MPEG-2 system and an MP HL decoder 5 demodulating an MP HL image, and a selector 9 that selects either one of output signals of the MP ML decoder 4, the MP HL decoder 5 and the 3OP-6OI conversion circuit 7 and outputs the signal.</p> |
