| 摘要 |
At the beginning of a test, a selector 22 selects and outputs a test clock CLKt provided by an LSI tester in conformance to a select signal SL. In response, test data are stored in an input data register 24 in synchronization with the clock CLKt. If the logic level of the select signal SL is changed after the test data are stored, the selector 22 selects an internal clock CLK generated by an internal oscillation circuit 21 and a core logic unit 23 generates output data through an operation performed in synchronization with the clock CLK. These output data are stored in an output data register 25. If the logic level of the select signal SL is changed after the output data are stored, the stored output data are output in synchronization with the clock CLKt.
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