发明名称 SAMPLE USING COMPLEMENTARY BIPOLAR TECHNOLOGY AND HOLDING DEVICE
摘要 PROBLEM TO BE SOLVED: To obstruct injection of disturbance caused by insulation of a transistor to an output sampling capacitor by providing a sample capacitor to which a copy of signal sampled is applied in addition to an output sampling capacitor. SOLUTION: In a holding mode, a sampling capacitor C makes voltage between a base and an emitter negative or zero, turns off a transistor Q1, and it is separated. As the transistor Q1 is turned off, accumulated electric charges are eliminated from the transistor Q1 by the base and the emitter. Thereby, as a pedestal part is generated by a part eliminated from an emitter out of electric charges of the transistor Q1, it is made constant independently of a level of input voltage, low distortion can be achieves, inverse polarity electric charges exist in two complementary transistors Q1, Q3 connected to the capacitor C, the difference is detected, a level of holding voltage is generated by only transistors Q1, Q3, thereby, being shifted to a holding mode once, voltage is generated at high speed.
申请公布号 JP2000311495(A) 申请公布日期 2000.11.07
申请号 JP20000074983 申请日期 2000.03.16
申请人 THOMSON CSF 发明人 SIMONY LAURENT
分类号 G11C27/02;H03K17/00;(IPC1-7):G11C27/02 主分类号 G11C27/02
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