| 摘要 |
According to one embodiment (100), a synchronous semiconductor memory may include a first initial circuit (102), second initial circuit (104) and third initial circuit (106). The first initial circuit (102) can receive an external clock signal CLK and compare the external clock signal CLK to a reference voltage VREF. The comparison result can be amplified and output as a signal phi 1. The second initial circuit (104) can receive a clock control signal CKE and compare the clock control signal CKE to a reference voltage VREF. The comparison result can be amplified and output as a signal phi 2. The third initial circuit (106) can receive the external clock signal CLK, and is activated by a control signal phi 7 that can correspond to the clock enable signal CKE. The third initial circuit (106) can compare the external clock signal CLK to a reference voltage VREF, and amplify and output the comparison result phi 8. The embodiment (100) can further include a first control circuit (108) that can receive the phi 1 signal and generate a period signal phi 3 having a constant pulse width that varies in synchronism with the external clock signal CLK. In addition, the first control circuit (108) can receive the phi 8 signal and generate an internal clock signal phi 5.
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