FERROELECTRIC RANDOM ACCESS MEMORY

摘要

PROBLEM TO BE SOLVED: To maintain the voltage difference between a first bit line and a second bit line, that is, a sensing margin constant even when power noise is generated during a read-out operation by simultaneously moving voltages on first and second bit lines and a plate line at the time of the generation of power noise. SOLUTION: A power node N1 supplying a power source voltage VCC to a first reference voltage supplying circuit 160 and a power node N2 supplying the power source voltage VCC to a second plate line driver are connected short as much as possible. Moreover, a power node N3 supplying the power source voltage VCC to a second reference voltage supplying circuit and a power node N4 supplying the power source voltage VCC to a first plate line driver 130 are connected short as much as possible. When power noise is generated during the read-out operation, a voltage on a bit line BLO-T receives an influence with the capacitor coupling structure of the voltage supplying circuit 160 and the sensing margin is secured.