| 摘要 |
Address decoder of the present invention includes a latch circuit for latching an address signal, a logical circuit for decoding output signal from the latching circuit and a decoding circuit for decoding an output signal from the logical circuit. The address signals are inputted to the latch circuit during a time period in which a clock signal is at a first level and latched during a time period in which the clock signal is at a second level. The logical circuits unconditionally initialize the output signal from the latch circuit when the clock signal being at first level.
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