发明名称 ARITHMETIC PROCESSOR
摘要 PROBLEM TO BE SOLVED: To efficiently process a CRC(cyclic redundancy check) operation by means of DSP(digital signal processor) by a little hardware investment. SOLUTION: Arithmetic equipment 104 executes the mod2 addition of MSB (most significant bit) of arithmetic data stored in an arithmetic data storage part 101 with input data stored in an in put data storage part 102. Arithmetic equipment 105 executes the mod2 addition of data obtained by shifting arithmetic data stored in the part 101 to an MSB side by one bit with a generation polynomial coefficient which is stored in a generation polynomial storage part 103. A selecting part 106 selects one of shift data and the arithmetic result of the equipment 105 based on the arithmetic result of the equipment 104 and the selected one is stored in the part 101 as new arithmetic data.
申请公布号 JP2000311096(A) 申请公布日期 2000.11.07
申请号 JP19990122673 申请日期 1999.04.28
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMANAKA RIYUUTAROU;SOUMON JUNJI;TODA TAKASHI
分类号 G06F11/10;G06F7/72;H03M13/00;H03M13/09;H04L1/00;(IPC1-7):G06F11/10 主分类号 G06F11/10
代理机构 代理人
主权项
地址