| 摘要 |
A synchronous semiconductor storage device (e.g., synchronous DRAM) contains a memory cell array consisting of memory cells, which are arranged in a matrix form in accordance with rows and columns. The memory cell array is accessed using row addresses and column addresses, which are made in synchronization with cycles of a clock signal being given from the external. When an active command is applied to the synchronous semiconductor storage device, a row address is designated so that a corresponding row of the memory cell array is activated. A first control signal is produced after a lapse of a predetermined delay time, which elapses from timing of the active command. A second control signal is produced after timing of a read command. In addition, a third control signal consisting of pulses is produced based on either the first control signal or second control signal which is delayed. A column address is designated in response to the third control signal, so that a specific memory cell is designated to enable a read operation. When a gap occurs in read operations so that the second control signal is delayed from the first control signal, a basis for creation of the third control signal is changed over from the first control signal to the second control signal. Incidentally, the first control signal is stopped in a period of time in which the third control signal is produced from the second control signal.
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