发明名称 TEST CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a test circuit having an effect for suppressing the cost of LSI production by eliminating a LSI test pin unnecessary for a normal operation. SOLUTION: When a shift register 7 and a control circuit 9 are reset by resetting or a control input 6, a test mode setting input pin 4 is connected to the shift register 7 by a selector 10. Then, a test mode signal is input by the test mode setting input pin 4, and its state is stored by the shift register 7. When a preset clock pulse number is achieved, an output 12 of the control circuit 9 changes for switching the selector 10 to connect the test mode setting input pin 4 to a connecting signal 14 for a circuit used for other use. An output of the shift register 7 is decoded by a decoder 8 and becomes a test mode output 11.
申请公布号 JP2000304831(A) 申请公布日期 2000.11.02
申请号 JP19990110759 申请日期 1999.04.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SATO TOMOYA;NAKAJIMA SHOTA
分类号 G01R31/28;G01R31/3185;(IPC1-7):G01R31/318 主分类号 G01R31/28
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