发明名称 CLOCK GENERATION CIRCUIT, SERIAL/PARALLEL CONVERTER AND PARALLEL/SERIAL CONVERTER, AND SEMICONDUCTOR DEVICE
摘要 <p>A clock generation circuit generates a polyphase output clock signal which can immediately follow a change of the period of an input clock signal. The clock generation circuit is provided with a voltage-controlled oscillator (14) for generating an output signal whose frequency varies with a control voltage, a phase comparator (11) for comparing the phase of the input clock signal and that of the output signal of the voltage-controlled oscillator and measuring the phase difference, a control-voltage generation circuit (12, 13) for generating a clock voltage that corresponds to the phase difference, and a variable delay circuit (15) for delaying the input clock signal according to the control signal and thereby generating the polyphase output clock signal.</p>
申请公布号 WO2000065717(P1) 申请公布日期 2000.11.02
申请号 JP2000002769 申请日期 2000.04.27
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