| 摘要 |
PROBLEM TO BE SOLVED: To stably shift the frequency of an output signal. SOLUTION: A frequency shift modulating circuit 100 is equipped with a DDS(direct digital synthesizer) 1 and a PLL 2. The DDS 1 stores frequency data showing the frequency of the output signal in a plurality of registers. The DDS 1 selects a register where the frequency data are stored according to an FSK(frequency shift keying) data signal having its voltage adjusted by a comparator 4. The signal outputted by the DSS 1 is inputted to the PLL 2. The PLL 2 generates a signal in phase with the signal received from the DDS 1 and outputs a frequency shift signal shifted in frequency corresponding to the digital value that the FSK data signal indicates. Further, the PLL 2 inputs the FSK data signal through a balance adjuster 5 and is capable of shifting the frequency greatly. With frequency data set to the DDS 1, even a low frequency can stably be modulated. |
