| 摘要 |
<p>A method and system for allowing back to back write operations utilizing a single port cache is disclosed. The method and system comprises overlapping and pipelining the tag lookup and data write instruction. In so doing, the processor would be able to perform single cycle cache hit detection/data write in a single port SRAM data cache. Two instructions can be operated on simultaneously without either of the two stages being idle. Accordingly, during the tag lookup cycle the data can be read while the data write cycle writes data. This simple pipelining procedure will allow the number of instruction cycles to be reduced down to only one cycle. Moreover, this methodology will work for consecutive read seek and data write to the same memory address as well.</p> |
