发明名称 TIMING OPTIMIZATION IN PRESENCE OF INTERCONNECT DELAYS
摘要 <p>A strategy for optimal buffering in the case of an infinitely long wire buffered with an arbitrary number of equally spaced single-size buffers is presented. A simple but efficient technique is proposed using this to choose a buffer size and determine a good inter-buffering distance up front, thus enabling fast, efficient buffer insertion. The analysis also allows representing delays of long wires as a simple function of the length and buffer and wire widths. Based on this, a novel constant wire delay approach is proposed where the proposed wire delay model is used for fairly accurate prediction of wire delays early in the design process and these predictions are later met via buffer insertion and wire sizing.</p>
申请公布号 WO2000065490(A1) 申请公布日期 2000.11.02
申请号 US2000011002 申请日期 2000.04.24
申请人 发明人
分类号 主分类号
代理机构 代理人
主权项
地址