发明名称 FABRICATION OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To enhance migration resistance of interconnection while suppressing increase of via resistance and avoiding open circuit of interconnection by suppressing the etching rate such that the upper part of a dummy plug is located at the same level as the bottom of interconnection or below at the point when an interconnection trench is formed. SOLUTION: An interlayer insulation film 5 which is different from a dummy plug 102 is deposited to cover the dummy plug 102 and then the upper surface is planarized. A photosensitive organic film is applied onto the interlayer insulation film 5 and then exposed and developed to form a second mask layer 6 having an opening 103 of same width as an interconnection trench 104. The interlayer insulation film 5 is etched using the second mask layer 6 as a mask to form the interconnection trench 104 and the upper surface of the dummy plug 102 is exposed to the bottom of the interconnection trench 104. Etching rate of the interlayer insulation film 5 is set lower than that of the dummy plug 102 so that the upper part of the dummy plug 102 does not project into the interconnection trench 104 when it is formed.
申请公布号 JP2000307003(A) 申请公布日期 2000.11.02
申请号 JP20000026840 申请日期 2000.02.03
申请人 NEC CORP 发明人 IKEDA MASAYOSHI
分类号 H01L21/768;H01L21/3205;(IPC1-7):H01L21/768;H01L21/320 主分类号 H01L21/768
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