| 摘要 |
The arrangement includes a digital filter formed through a predetermined amount of delay elements (T) and multipliers (M), whereby filter coefficients (k) are determined by device of an adjustment algorithm, and the delayed signals are multiplied with the filter coefficient and are added up. A memory (FIFO1) for the temporary storage of at least one burst-like signal (x(nT)) is connected in series with the filter. The filter comprises preferably a digital feedback branch (RK), formed also through a predetermined amount of delay elements and multipliers. The memory is preferably implemented as a FIFO memory.
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