发明名称 ERROR CORRECTION AND DECODING SYSTEM AND DEVICE
摘要 PROBLEM TO BE SOLVED: To provide an error correction and decoding system which corrects an error without using division operation on a finite body by using the property of zef logarithm as the element technology of a decoding process part for error correction code and can reduce a circuit scale. SOLUTION: This decoding system eliminates division operation by applying zef logarithm to corrected-version Peterson algorithm as decoding algorithm for Reed-Solomon code, constitutes zef logarithm in nest-like structure as to a chain search which makes an error position search to reduce the circuit scale, a actualizes an efficient error correction by using a memory 506.
申请公布号 JP2000307436(A) 申请公布日期 2000.11.02
申请号 JP19990107543 申请日期 1999.04.15
申请人 HITACHI LTD 发明人 MORIYASU TAKASHI
分类号 G11B20/18;H03M13/00;H04L1/00;(IPC1-7):H03M13/00 主分类号 G11B20/18
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