CIRCUIT DEVICE FOR INITIALIZATION WITHOUT INTERRUPTION OF DELAY CLOCK LOOP CIRCUIT BY HIGH SPEED LOCKING

摘要

PROBLEM TO BE SOLVED: To avoid the instability of a counter value owing to the inactivation of a counter control signal by delaying a control signal and holding the delayed control signal for prescribed time with the rise edge of a counter clock signal. SOLUTION: A delay circuit 15 delays a clock signal. The clock signal and a signal obtained by delaying the clock signal have same frequencies and the delayed clock signal is delayed and generated. The delayed clock signals are supplied to transmission gates 16 and 17 opened by logic '0' and '1'. The gate 17 is installed in the signal line of a control signal and an output side is connected to an inverter 20 through an NOR gate 18 or through the transmission gate 16 and an inverter 19, The delayed control signal is obtained in the output side. The control signal is transparently switched to the delayed control signal while the delayed clock signal is logic '1' or high. While the delayed clock signal is logic '0' or low, the delayed clock signal is used for holding the delayed control signal for prescribed time.