| 摘要 |
PROBLEM TO BE SOLVED: To provide an image reader which adjusts the input timing of a clock highly accurately without changing hardware, in the case of changing image sensors and the input timing of a drive (sampling) clock in an ADC that performs A/D conversion of its image output. SOLUTION: The phase of a driver clock is adjusted by setting adjustment data from a CPU 101 to the register of a timing circuit 112, which outputs an ADCLK for sampling to ADCs (R, G and B) 119 to 121, outputs an ICLK and a three-line CCD 111 to an image processing system and outputs a drive clock to an analog processing system, etc. White reference is used in an adjustment operation mode, a digital value detection circuit 122 is served also as a shading correction circuit and a memory detects outputs of the ADCs 119 to 121 of each phase obtained, by shifting an image clock by a reciprocal of the integral multiples, and the input timing of the clock is adjusted by evaluating the value, selecting an optimum phase and setting it as adjustment data.
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