| 摘要 |
PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device which is enhanced in degree of integration or lessened in chip size by a method wherein an upper and a lower auxiliary signal wire are laid out in accordance with a prescribed wiring pattern. SOLUTION: A lower backing wiring 23 is provided on a gate wiring 21 through the intermediary of an insulating layer 22, and an upper backing wiring 25 is formed thereon through the intermediary of an insulating layer 24. Contacts 28 between a gate wiring 21 and the upper backing wiring 25 are dispersedly arranged on one or more different straight lines which extend in a direction vertical to the direction in which the gate wiring 21 extends, and the adjacent contacts 28 out of the contacts 28 are each arranged on the different straight lines. The lower backing wiring 23 is made to pass through between the adjacent contacts 28. |
