| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide an asynchronous signal interface circuit with a simple circuit configuration and capable of sure data transfer. SOLUTION: After a reset signal RST is released, input data DI are latched by a FF(flip-flop) 12 at a first leading of an input clock signal CLK1 and latched by a FF 11 respectively at a 2nd leading. On the other hand, a selection signal SEL is switched to 'H' at a first leading of an output clock signal CLK2 and 'L' at a 2nd leading respectively. Thus, a selector 14 selects newest latched data DA, DB in the FFs 11, 12 and latched by a FF 16 synchronously with the output clock signal CLK2 and outputted as output data DO.</p> |
